4 : 2 Decoder Design using Logical Gates (Data Flow Modeling Style)-
Verilog CODE -
//-----------------------------------------------------------------------------
//
// Title : encoder4_2
// Design : verilog upload
// Author : Naresh Singh Dobal
// Company : nsd
//
//-----------------------------------------------------------------------------
//
// File : 4 to 2 Encoder Design using Logical Gates.v
module encoder4_2 ( a ,b ,c ,d ,x ,y );
output x ;
output y ;
input a ;
input b ;
input c ;
input d ;
assign x = b | d;
assign y = c | d;
endmodule
 |
| Output Waveform : 4 : 2 Decoder |
Verilog CODE -
//-----------------------------------------------------------------------------
//
// Title : encoder4_2
// Design : verilog upload
// Author : Naresh Singh Dobal
// Company : nsd
//
//-----------------------------------------------------------------------------
//
// File : 4 to 2 Encoder Design using Logical Gates.v
module encoder4_2 ( a ,b ,c ,d ,x ,y );
output x ;
output y ;
input a ;
input b ;
input c ;
input d ;
assign x = b | d;
assign y = c | d;
endmodule
why is the input 'a' never used?
ReplyDeletewhy is the input 'a' never used?
ReplyDeletewhy is the input 'a' never used?
ReplyDeletethank you sir for your wonderful work
ReplyDeletethank you
ReplyDeletethank you
ReplyDeleteSend Bob and vagene
ReplyDeleteSir thanks
ReplyDeleteSir nanum Naresh dha sir
ReplyDeleteQ. why is the input 'a' never used?
ReplyDeleteA. Use K-map for 4 to 2 encoder, you will get x=b+d , y=c+d.