Small Description about Data Flow Modeling Style in Verilog HDL.

Data Flow modeling style—

Data flow modeling style shows how the data flow from input to output threw the registers / components.

Data Flow Modeling Style works on Concurrent Executions.

Concurrent Statements in Verilog HDL-

Concurrent Signal Assignment   (Assign).

Conditional Operator  ( ?  :  ).

Sample Programs of Data Flow Modeling Style-

Digital System Design using Logical Expressions (Program List)-

• Simple AND Gate Design using Verilog HDL.
• Logical Operators Test in Verilog HDL.
• Half Adder Design Using Logical Expression (Verilog HDL Code).
• Full Adder Design Using Logical Expression (Verilog HDL Code).
• 4 : 1 Multiplexer Design using Logical Expressions (Verilog HDL Code).
• 1 : 4 Demultiplexer Design using Logical Gates (Verilog HDL Code).
• 2 : 4 Decoder Design using Logical Gates (Verilog HDL Code).
• 4 : 2 Encoder Design using Logical Gates (Verilog HDL Code).
• Half Subtractor Design using Logical Expression  (Verilog HDL Code).
• Full Subtractor Design using Logical Gates (Verilog HDL Code).
• Design of 1 bit Comparator using Logical Gates (Verilog HDL Code).
• Design of Binary to Gray Converter using Data Flow Modeling Style).
• Design of Gray to Binary Converter using Logical Gates (Verilog HDL Code).

Digital System Design using Conditional Operator (Program List)-

• Design of 4 : 1 Multiplexer using Conditional Operator (Data Flow Modeling Style).
• Design of 1 : 4 Demultiplexer using Conditional Operator (Data Flow Modeling Style).
• Design of 4 : 2 Encoder using Conditional Operator (Data Flow Modeling Style).
• Design of 2 : 4 Encoder using Conditional Operator (Data flow Modeling Style).
• Design of Binary to Excess3 Code Converter using Conditional Operator (Data Flow Modeling Style).
• Design of BCD to 7 Segment Driver For Common Cathode using Conditional Operator.
• Design of BCD to 7 Segment Driver For Common Anode using Conditional Operator.
• Design of 2 Bit Comparator Using Conditional Operator.