Design of BCD Counter using Behavior Modeling Style -
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| Output Waveform : BCD Counter |
Verilog CODE -
//-----------------------------------------------------------------------------
//
// Title : BCD_Counter
// Design : verilog upload 4
// Author : Naresh Singh Dobal
// Company : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File : Design of BCD Counter using Behavior Modeling Style.v
module BCD_Counter ( clk ,reset ,dout );
output [3:0] dout ;
reg [3:0] dout ;
input clk ;
wire clk ;
input reset ;
wire reset ;
initial dout = 0 ;
always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else if (dout<=9) begin
dout <= dout + 1;
end else if (dout==9) begin
dout <= 0;
end
end
endmodule
appreciate your answer but i found an error.
ReplyDeletewhen the counter counts to 9 it is supposed to come back to 0 but the code you've provided doesn't do so
this is the corrected code:
module BCD_Counter ( clk ,reset ,dout );
output [3:0] dout ;
reg [3:0] dout ;
input clk ;
wire clk ;
input reset ;
wire reset ;
initial dout = 0 ;
always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else if (dout<9) begin
dout <= dout + 1;
end else if (dout==9) begin
dout <= 0;
end
end
endmodule
Isn't this just a mod 9 counter . Isn't a BCD counter be one that should be able to drive a BCD display ??
ReplyDeletehow can i implement a code for bcd counter on 7 segment counting up to 59 minutes including seconds too ?!
ReplyDeleteSagin mod 9 counter is nothing but BCD counter
ReplyDeleteIs it asynchronous reset
ReplyDelete