Design of Frequency Divider (Divide by 10) using Behavior Modeling Style (Verilog CODE) -

Design of Frequency Divider (Divide by 10) using Behavior Modeling Style -

Output Waveform :   Frequency Divider (Divide by 10).

Verilog CODE -



//-----------------------------------------------------------------------------
//
// Title       : frquency_divider_by10
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Design of frequency Divider (divide by 10).v


module frquency_divider_by10 ( clk ,out_clk );

output out_clk ;
reg out_clk ;

input clk ;
wire clk ;

reg [3:0] m;

initial m = 0;

always @ (posedge (clk)) begin
if (m<9)
m <= m + 1;
else
m <= 0;
end

always @ (m) begin
if (m<5)
out_clk <= 1;
else
out_clk <= 0;
end


endmodule