Digital System Design using Logical Expression (Verilog CODE).

Digital System Design using Logical Expression (Data Flow Modeling Style)-



Sample Codes -

• Simple AND Gate Design using Verilog HDL.
• Logical Operators Test in Verilog HDL.
• Half Adder Design Using Logical Expression (Verilog HDL Code).
• Full Adder Design Using Logical Expression (Verilog HDL Code).
• 4 : 1 Multiplexer Design using Logical Expressions (Verilog HDL Code).
• 1 : 4 Demultiplexer Design using Logical Gates (Verilog HDL Code).
• 2 : 4 Decoder Design using Logical Gates (Verilog HDL Code).
• 4 : 2 Encoder Design using Logical Gates (Verilog HDL Code).
• Half Subtractor Design using Logical Expression  (Verilog HDL Code).
• Full Subtractor Design using Logical Gates (Verilog HDL Code).
• Design of 1 bit Comparator using Logical Gates (Verilog HDL Code).
• Design of Binary to Gray Converter using Data Flow Modeling Style).
• Design of Gray to Binary Converter using Logical Gates (Verilog HDL Code).