
A Small Discussion about VHDL & Verilog HDL -
VHDL or Verilog HDL - A small discussion (Verilog HDL with Naresh Singh Dobal learning Series).
Verilog HDL is easier to understand and use, It is very effectively used for
simulation and synthesis. but it lacks for system level or complex designing.
It is promoted by OVI (Open Verilog International). It is widely used for ASIC
designing or lower level design (RTL or lower), but this results in
faster simulation and effective synthesis. Mostly used in North America, Asia
& Japan, but not popular in Europe.
As comparable to verilog HDL, VHDL is more complex, thus difficult to learn
and use. But this offers more flexibility of designing. Since VHDL is better
suited...