Design of JK Flip Flop using Behavior Modeling Style (Verilog CODE) -

Design of JK Flip Flop using Behavior Modeling Style -

Output Waveform :   JK Flip Flop

Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : JK_flip_flop
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : JK flip flop using Behavior Modeling Style.v



module JK_flip_flop ( j ,k ,clk ,reset ,q ,qb );

output q ;
reg q ;
output qb ;
reg qb ;

input j ;
wire j ;
input k ;
wire k ;
input clk ;
wire clk ;
input reset ;
wire reset ;

always @ (posedge (clk)) begin
if (reset) begin
q <= 0;
qb <= 1;
end
else begin
if (j!=k) begin
q <= j;
qb <= k;
end
else if (j==1 && k==1) begin
q <= ~q;
qb <= ~qb;
end
end
end


endmodule