Chip / FPGA Design Flow

FPGA   Design Flow –

 

FPGA Design Flow (Learn Verilog HDL with Naresh Singh Dobal Series).

Design Specification – Design specification is the state at which we define the important parameters like – consider a system / design of counter then specify start point, end point, length of counter, should have synchronous reset, reset is at logic high, at reset output should be ‘0’ etc.

Design specification include Market Requirement Documents (MRD Sheet), High Level Design, Low / Micro Level Design and RTL Coding Part.

Design specification process starts from the MRD Sheet (Market Requirement Documents), This outlines the requirements of a new product. This section covers the market needs, the customer value proposition, and product functionality. It is developed by the marketing team and upper level management.

High Level Design (HLD) -   At this state we defined all the major blocks of any complex system and also defines how they communicate or connected to each other like consider a microcontroller then the major block ay be RAM, ROM, Micro-Processor, Timer, Ports, ADC, Counters, etc.

Low Level Design (LLD) -  At this state we describes that how all major blocks of main system / design will be implement. It contains details of State Machines, Counters, MUX, Decoders, Internal registers etc. This phase need a lot of time to implement.

RTL Coding  -  At this stage we convert our micro design into HDL (VHDL / Verilog HDL) code using synthesizable constructs of language. This part consist of coding.

In real life RTL Code means that how the small modules and components are connected to each other or how data flows threw registers but in HDL language any code or collection of statements that are synthesizable are called RTL code.

Design Simulation  -  Simulation is the process of verifying the functional specification of system. We use simulators for simulation purpose. To test weather the RTL code meets the functional specification or not, we must see all the RTL block are functioning correctly with all the possibilities. For that purpose we use test benches. This takes 60 – 70 %of time in design verification. 

Design Simulation : Learn Verilog HDL with Naresh Singh Dobal Series

Simulation are mainly two types.

First is Functional Simulation or Behavior Simulation – Functional simulation is the verification of functionality in the term of waveforms without considering timing specification.

Timing Simulation or SDF Simulation – Timing simulation also called Gate level simulation needs complete synthesis, place and route and timing details. In Timing simulation we consider all the timing and other parameters for real time simulation by considering delay of all Gate level netlist.

Synthesis -  Synthesis is the process in which synthesis tool like design compiler (Xilinx XST or vivado etc), take RTL in Verilog or VHDL, and convert that code into the Register Level Netlist according to target technology.

Design Synthesis : Learn Verilog HDL with Naresh Singh Dobal Series.

Formal Verification – Check if the RTL to gate mapping is correct.

Scan Insertion – Insert the scan chain in case of ASIC.

Place & Route -  The gate – level netlist from the synthesis tool is taken and imported into place & route tool in verilog or vhdl netlist format, all the flip flops and gates are placed and routed according to place and route (PNR) tool, P&R tool generate GDS file used by foundry for ASIC Verification.

Configuration - This is the Implementation stage where we configure our FPGA Devices according to our requirement or RTL Structures. Now the configured device ready for real life testing and application use.

Post Sil. Validation – Once the chip is back from fabrication, It need to put in real environment for testing before sending it to market. Se we need post silicon validation step.

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My name is “Naresh Singh Dobal”, for any query you can write us directly at     nsdobal@gmail.com