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Design of Parallel In - Serial OUT Shift Register using Behavior Modeling Style -
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| Output Waveform : Parallel IN - Serial OUT Shift Register |
Verilog CODE -
//-----------------------------------------------------------------------------
//
// Title : parallel_in_serial_out
// Design : vhdl_upload2
// Author : Naresh Singh Dobal
// Company : nsdobal@gmail.com
// Verilog HDL Programs & Exercise with Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File : Parallel IN - Serial OUT Shift Register.v
module parallel_in_serial_out ( din ,clk ,reset ,load ,dout );
output dout ;
reg dout ;
input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
input load ;
wire load ;
reg [3:0]temp;
always @ (posedge (clk)) begin
if (reset)
temp <= 1;
else if (load)
temp <= din;
else begin
dout <= temp[3];
temp <= {temp[2:0],1'b0};
end
end
endmodule
9 comments :
plzz give the testbench code for this...
plzz write the same code to run for 8 times
Pl. correct the code. When reset signal is high then temp variable should be loaded with Zero not one.
would you please explain why temp <= {temp[2:0],1'b0}; line is used.
see it,temp is operating left shift and input is given zero in 0th position.
What is the structural module for PISO
would you please explain why temp <= {temp[2:0],1'b0}; line is used.
don't use the line,
temp <= {temp[2:0],1'b0};
instead use
temp <= temp<<1;
above line shifts the registers to temp[3] location from temp[2:0]
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