Tuesday, 12 November 2013

A Small Discussion about VHDL & Verilog HDL...

A Small Discussion about VHDL & Verilog HDL -

VHDL or Verilog HDL - A small discussion (Verilog HDL with Naresh Singh Dobal learning Series).

Verilog HDL is easier to understand and use, It is very effectively used for simulation and synthesis. but it lacks for system level or complex designing. It is promoted by OVI (Open Verilog International). It is widely used for ASIC designing or lower level design (RTL or  lower), but this results in faster simulation and effective synthesis. Mostly used in North America, Asia & Japan, but not popular in Europe.

As comparable to verilog HDL, VHDL is more complex, thus difficult to learn and use. But this offers more flexibility of designing. Since VHDL is better suited for handling very complex systems, so it is now gaining popularity. VHDL  is mainly promoted by VHDL international. VHDL is relatively weaker in lower designs. But superior in system level design. Many believes that in long terms presents better condition and adaptability than its competitors. This language is widely used in Europe, significantly used in US and Canada, but this disliked in Japan...

Both the HDL's are used to describe electronic systems.
The function of systems is to get input data from it's environment and give output some data in return.
In verilog HDL this is called a module which is a basic building block in Verilog HDL, and in VHDL this is defined in Entity & Architecture Pair.
 Both the Languages are IEEE Standard.

I would love to read your suggestions and comments here below,
Best Regard //
Naresh Singh Dobal

Monday, 11 November 2013

Basics of Verilog HDL Language Execution Process (Concurrent and Sequential) -

Basics of Verilog HDL Language Executioin Process (Concurrent and Sequential). -

Basics of Verilog HDL Language Execution Process (Verilog HDL with Naresh Singh Dobal learning Series)

Hello Friends,
       Before start writing of codes in Verilog HDL for digital systems you must know about the execution of Verilg HDL language, you should know that how the tools process the Verilog HDL code. This is a very important concept you should understand for proficiency in Verilog HDL.

Verilog HDL can be programmed in following execution pattern.
1.Concurrent Execution.
2.Sequential Execution.
Verilog HDL can work on –
1.Concurrent Language.
2.Sequential Language.
3.Net-List Language.
4.Timing Specification.
5.Waveform Generation Language.
Before describing all above language I want to ask a question to you…….This will help you to understand the concept.
My question is, -  Suppose we have a real life IC and we are using that in a hardware circuit and we have four inputs and four outputs in IC, so is it possible to give inputs one by one I mean is it possible to give it input to first pin and others are idle or after some time input switch to second pin. And so on…………………. Is it ??????????
Answer is No, Obviously this is not possible in real life, If one IC having four inputs and then we have to give all the inputs in same time, doesn’t matter our inputs are affecting the outputs or not. But we have to give all the inputs to all pins at a same time.

That means we can easily say that all the real life IC working on concurrent fashion. And all our HDL tools are also performs concurrent execution to get real life working environment. And we have to define all the connections of gates and Registers threw nets, or we must define the flow of data from input to output. But in that manner we must know the structure of hardware system. This is a very difficult task for designers for complex system. As we know today we have multi-billion transistors in a single IC chip, so this is practically impossible to design a complete system in term of structure.  

In solution of that probelm designer prefer Sequential Language.
Next is Sequential Execution -
I am going to start describing this with the most widely used execution process which is used in multiple languages. If we talk about software languages most of them are worked on Sequential processing or line by line processing concept. VHDL or Verilog HDL both are working on Sequential language as well. This makes our designing process very easy, because using of different sequential concepts like if-else, case, loops, edge-triggering etc. so now if we have to design a 4 bit comparator we just write     

If (a=b) then
    eq <= ‘1’;
   eq <= ‘0’;
End if;

** where a and b are 4 bit inputs and eq is 1 bit output.
But my question to you is, how you define a sequential language with a hardware part. Because in sequential execution statements will perform according to line by line, and in hardware all process should be taken at same time. So how we configure our system (designed using sequential execution) in real life hardware……..???????

Let me explain –
Firt you should know what is configured in our hardware, We code our system in HDL (concurrent + sequential) but that hdl code never configured with hardware, what is configured – RTL, that means we have to convert our HDL code into RTL structure before configuring. Which provide physical connection of all physical registers. Registers which I have defined in my previous post (individual basic gate or a combination of gates).

** Also remember normally all our HDL's perform concurrent execution, If some one ask you that Verilog HDL is basically what type of language then answer is -
Verilog HDL is Concurrent type of language, but it supports Sequential language as well.
and If we need sequential language anywhere then we convert our execution from concurrent to sequential, later I will tell you how we convert the way of execution and what keywords designers use for that purpose.
Now I believe that you understand both the executions i.e, concurrent or sequential.

Net list language –
Net list language is also working on Concurrent execution. But only the difference is in net list language we design our system by defining the basic elements like gates or collection of gates (called modules and registers). 

Above three languages are used for designing purpose.

Other two languages i.e. Timing specification and  waveform generation language are used for verification purpose. In brief -

Timing Specification -  we can define the flow of data from input to output in our simulation screen but again this can not be implement in real life hardware because you can't specify the time of flow of data. So timing specification language only use in writing of test benches. Same a waveform generation language, Is used for creation of waveforms, basically this is a  algorithm to get the same output by minimizing the processing time.

For more information you can go with our video tutorial series.
I would love to read your comments and suggestions in comment bar below…
My name is “Naresh Singh Dobal”, for any query you can write us directly at     nsdobal@gmail.com

Friday, 8 November 2013

Chip / FPGA Design Flow

FPGA   Design Flow –

FPGA Design Flow (Learn Verilog HDL with Naresh Singh Dobal Series).

Design Specification – Design specification is the state at which we define the important parameters like – consider a system / design of counter then specify start point, end point, length of counter, should have synchronous reset, reset is at logic high, at reset output should be ‘0’ etc.

Design specification include Market Requirement Documents (MRD Sheet), High Level Design, Low / Micro Level Design and RTL Coding Part.

Design specification process starts from the MRD Sheet (Market Requirement Documents), This outlines the requirements of a new product. This section covers the market needs, the customer value proposition, and product functionality. It is developed by the marketing team and upper level management.

High Level Design (HLD) -   At this state we defined all the major blocks of any complex system and also defines how they communicate or connected to each other like consider a microcontroller then the major block ay be RAM, ROM, Micro-Processor, Timer, Ports, ADC, Counters, etc.

Low Level Design (LLD) -  At this state we describes that how all major blocks of main system / design will be implement. It contains details of State Machines, Counters, MUX, Decoders, Internal registers etc. This phase need a lot of time to implement.

RTL Coding  -  At this stage we convert our micro design into HDL (VHDL / Verilog HDL) code using synthesizable constructs of language. This part consist of coding.

In real life RTL Code means that how the small modules and components are connected to each other or how data flows threw registers but in HDL language any code or collection of statements that are synthesizable are called RTL code.

Design Simulation  -  Simulation is the process of verifying the functional specification of system. We use simulators for simulation purpose. To test weather the RTL code meets the functional specification or not, we must see all the RTL block are functioning correctly with all the possibilities. For that purpose we use test benches. This takes 60 – 70 %of time in design verification. 

Design Simulation : Learn Verilog HDL with Naresh Singh Dobal Series

Simulation are mainly two types.

First is Functional Simulation or Behavior Simulation – Functional simulation is the verification of functionality in the term of waveforms without considering timing specification.

Timing Simulation or SDF Simulation – Timing simulation also called Gate level simulation needs complete synthesis, place and route and timing details. In Timing simulation we consider all the timing and other parameters for real time simulation by considering delay of all Gate level netlist.

Synthesis -  Synthesis is the process in which synthesis tool like design compiler (Xilinx XST or vivado etc), take RTL in Verilog or VHDL, and convert that code into the Register Level Netlist according to target technology.

Design Synthesis : Learn Verilog HDL with Naresh Singh Dobal Series.

Formal Verification – Check if the RTL to gate mapping is correct.

Scan Insertion – Insert the scan chain in case of ASIC.

Place & Route -  The gate – level netlist from the synthesis tool is taken and imported into place & route tool in verilog or vhdl netlist format, all the flip flops and gates are placed and routed according to place and route (PNR) tool, P&R tool generate GDS file used by foundry for ASIC Verification.

Configuration - This is the Implementation stage where we configure our FPGA Devices according to our requirement or RTL Structures. Now the configured device ready for real life testing and application use.

Post Sil. Validation – Once the chip is back from fabrication, It need to put in real environment for testing before sending it to market. Se we need post silicon validation step.

I would love to read your comments and suggestions in comment bar below…

My name is “Naresh Singh Dobal”, for any query you can write us directly at     nsdobal@gmail.com


What a Designer can do using Verilog HDL -

What a Designer can do using Verilog HDL -

What a Designer can do using VerilogHDL : (Learn Verilog HDL with Naresh Singh Dobal series).

Now next thing is What you we do with the Help of HDL’s-
So here I can say that you can design a complete electronics part of any system with the help of HDL’s, You can design any type of circuits like a complete robot system design, a home automation system, security system, life style appliances, Industry automation system, PLC’s etc, You can design a microprocessor or a microcontroller of your own configuration according to your requirement, you can design a computer on chip etc.
Second most widely used application of HDL’s are you can directly configure your design or system on Hardware with the help of PLD’s, There are multiple type and class of PLD’s like PAL (Programmable Array Logic), PLA (Programmable Logical Array). SPLD (Simple Programmable Logical Devices), CPLD (Complex Programmable Logical Devices),
PROM (Programmable ROM), FPGA (Field Programmable Gate Array), ASIC ( Application Specific Integrated Circuit). Among these FPGA & ASIC are widely used for configuration. That means with the help of FPGA devices we can directly configure our system on Hardware and can test our design in real time environment.

I would love to read your comments and suggestions in comment bar below…
My name is “Naresh Singh Dobal”, for any query you can write us directly at     nsdobal@gmail.com

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