Monday 15 July 2013

4 to 1 Multiplexer Design using Logical Expression (Verilog CODE)

4 to 1 Multiplexer Design using Logical Expression  (Data Flow Modeling Style)-


Output Waveform : 4 to 1 Multiplexer

Program -



//-----------------------------------------------------------------------------
//
// Title       : multiplexer4_1
// Design      : vhdl_test
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : 4 : 1 Multiplexer using Logical Expression.v



module multiplexer4_1 ( a ,b ,c ,d ,x ,y ,dout );

output dout ;

input a ;
input b ;
input c ;
input d ;
input x ;
input y ;

assign dout = (a & (~x) & (~y)) |
 (b & (~x) & (y)) |
 (c & x & (~y)) |
 (d & x & y);

endmodule

1 comments :

Unknown said...

Hello Naresh could u tell me how to implement multiplexer with active low output?

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