Tuesday, 23 July 2013

Design of 4 Bit Binary Counter using Behavior Modeling Style (Verilog CODE) -






Design of 4 Bit Binary Counter using Behavior Modeling Style -


Output Waveform :    4 Bit Binary Counter



Verilog CODE -



//-----------------------------------------------------------------------------
//
// Title       : Counter_4Bit
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Design of 4 Bit Counter using Behavior Modeling Style.v


module Counter_4Bit ( clk ,reset ,dout );

output [3:0] dout ;
reg [3:0] dout ;

input clk ;
wire clk ;
input reset ;
wire reset ;

initial dout = 0;

always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else
dout <= dout + 1;
end


endmodule

6 comments :

Devi Priya said...

Will you please provide the explanation also...?

Devi Priya said...

Will you please provide the explanation also...?

saikiran hrinarthini said...

will u please provide the test bench for it?

ธนารักษ์ รักษี said...

module Counter_4BitTestBench;
reg clk;
reg reset;
wire [3:0] dout ;
parameter step = 100;
Counter_4Bit uut (clk, dout , reset);
always begin
clk = 0; #(step/2);
clk = 1; #(step/2);
end
initial begin
reset = 0;
#step reset = 1;
#(step*20) $finish;
end
initial $monitor($stime," clk = %b, reset = %b, dout = %h",clk,reset,dout );


endmodule

Mert SURUCUOGLU said...
This comment has been removed by the author.
Unknown said...

Need verilog code for a counter which counts the given sequence

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