Monday, 15 July 2013

Full Subtractor Design using Logical Gates (Verilog CODE)

Full Subtractor Design using Logical Gates (Data Flow Modeling Style)-


Output Waveform : Full Subtractor

Program-



//-----------------------------------------------------------------------------
//
// Title       : full_subtractor
// Design      : vhdl_test
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : Full Subtractor Design using Logical Expression.v



module full_subtractor ( a ,b ,c ,diff ,borrow );

output diff ;
output borrow ;

input a ;
input b ;
input c ;

assign diff = a ^ b ^ c;
assign borrow = ((~a) & b) | (b & c) | (c & (~a));

endmodule

1 comments :

Unknown said...

Can this be extended to 16 bit?

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