Monday, 11 November 2013

Basics of Verilog HDL Language Execution Process (Concurrent and Sequential) -

Basics of Verilog HDL Language Executioin Process (Concurrent and Sequential). -

Basics of Verilog HDL Language Execution Process (Verilog HDL with Naresh Singh Dobal learning Series)

Hello Friends,
       Before start writing of codes in Verilog HDL for digital systems you must know about the execution of Verilg HDL language, you should know that how the tools process the Verilog HDL code. This is a very important concept you should understand for proficiency in Verilog HDL.

Verilog HDL can be programmed in following execution pattern.
1.Concurrent Execution.
2.Sequential Execution.
Verilog HDL can work on –
1.Concurrent Language.
2.Sequential Language.
3.Net-List Language.
4.Timing Specification.
5.Waveform Generation Language.
Before describing all above language I want to ask a question to you…….This will help you to understand the concept.
My question is, -  Suppose we have a real life IC and we are using that in a hardware circuit and we have four inputs and four outputs in IC, so is it possible to give inputs one by one I mean is it possible to give it input to first pin and others are idle or after some time input switch to second pin. And so on…………………. Is it ??????????
Answer is No, Obviously this is not possible in real life, If one IC having four inputs and then we have to give all the inputs in same time, doesn’t matter our inputs are affecting the outputs or not. But we have to give all the inputs to all pins at a same time.

That means we can easily say that all the real life IC working on concurrent fashion. And all our HDL tools are also performs concurrent execution to get real life working environment. And we have to define all the connections of gates and Registers threw nets, or we must define the flow of data from input to output. But in that manner we must know the structure of hardware system. This is a very difficult task for designers for complex system. As we know today we have multi-billion transistors in a single IC chip, so this is practically impossible to design a complete system in term of structure.  

In solution of that probelm designer prefer Sequential Language.
Next is Sequential Execution -
I am going to start describing this with the most widely used execution process which is used in multiple languages. If we talk about software languages most of them are worked on Sequential processing or line by line processing concept. VHDL or Verilog HDL both are working on Sequential language as well. This makes our designing process very easy, because using of different sequential concepts like if-else, case, loops, edge-triggering etc. so now if we have to design a 4 bit comparator we just write     

If (a=b) then
    eq <= ‘1’;
   eq <= ‘0’;
End if;

** where a and b are 4 bit inputs and eq is 1 bit output.
But my question to you is, how you define a sequential language with a hardware part. Because in sequential execution statements will perform according to line by line, and in hardware all process should be taken at same time. So how we configure our system (designed using sequential execution) in real life hardware……..???????

Let me explain –
Firt you should know what is configured in our hardware, We code our system in HDL (concurrent + sequential) but that hdl code never configured with hardware, what is configured – RTL, that means we have to convert our HDL code into RTL structure before configuring. Which provide physical connection of all physical registers. Registers which I have defined in my previous post (individual basic gate or a combination of gates).

** Also remember normally all our HDL's perform concurrent execution, If some one ask you that Verilog HDL is basically what type of language then answer is -
Verilog HDL is Concurrent type of language, but it supports Sequential language as well.
and If we need sequential language anywhere then we convert our execution from concurrent to sequential, later I will tell you how we convert the way of execution and what keywords designers use for that purpose.
Now I believe that you understand both the executions i.e, concurrent or sequential.

Net list language –
Net list language is also working on Concurrent execution. But only the difference is in net list language we design our system by defining the basic elements like gates or collection of gates (called modules and registers). 

Above three languages are used for designing purpose.

Other two languages i.e. Timing specification and  waveform generation language are used for verification purpose. In brief -

Timing Specification -  we can define the flow of data from input to output in our simulation screen but again this can not be implement in real life hardware because you can't specify the time of flow of data. So timing specification language only use in writing of test benches. Same a waveform generation language, Is used for creation of waveforms, basically this is a  algorithm to get the same output by minimizing the processing time.

For more information you can go with our video tutorial series.
I would love to read your comments and suggestions in comment bar below…
My name is “Naresh Singh Dobal”, for any query you can write us directly at


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