Monday, 15 July 2013

1 : 4 Demultiplexer Design using Gates (Verilog CODE).

1 : 4   Demultiplexer Design using Logical Gates (Data Flow Modeling Style)-


Output WaveForm : 1 : 4 Demultiplexer


Program-


//-----------------------------------------------------------------------------
//
// Title       : demultiplexer1_4
// Design      : vhdl_test
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : 1 : 4 Demultiplexer using Logical Expression.v



module demultiplexer1_4 ( din ,x ,y ,a ,b ,c ,d );

output a ;
output b ;
output c ;
output d ;

input din ;
input x ;
input y ;

assign a = din & (~x) & (~y);
assign b = din & (~x) & y;
assign c = din & x & (~y);
assign d = din & x & y;

endmodule

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