Sunday, 21 July 2013

Design of JK Flip Flop using Behavior Modeling Style (Verilog CODE) -






Design of JK Flip Flop using Behavior Modeling Style -


Output Waveform :   JK Flip Flop


Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : JK_flip_flop
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : JK flip flop using Behavior Modeling Style.v



module JK_flip_flop ( j ,k ,clk ,reset ,q ,qb );

output q ;
reg q ;
output qb ;
reg qb ;

input j ;
wire j ;
input k ;
wire k ;
input clk ;
wire clk ;
input reset ;
wire reset ;

always @ (posedge (clk)) begin
if (reset) begin
q <= 0;
qb <= 1;
end
else begin
if (j!=k) begin
q <= j;
qb <= k;
end
else if (j==1 && k==1) begin
q <= ~q;
qb <= ~qb;
end
end
end


endmodule

3 comments :

Prajwal Dsouza said...

This code doesn't work..i used Xilinx bu the way. Whatever the case, it doesn't work in toggle condition at all...

Prajwal Dsouza said...

This code doesn't work..i used Xilinx bu the way. Whatever the case, it doesn't work in toggle condition at all...

Unknown said...

made my day bro

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