Saturday 20 July 2013

Design of 4 to 1 Multiplexer using if -else statement (Behavior Modeling Style) Verilog CODE-






Design of 4 to 1 Multiplexer using if - else statement (Behavior Modeling Style) -



Output Waveform :   4 to 1 Multiplexer



Verilog CODE -



//-----------------------------------------------------------------------------
//
// Title       : multiplexer4_1
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : 4 to 1 multiplexer using if else statements.v



module multiplexer4_1 ( din ,sel ,dout );

output dout ;
reg dout ;

input [3:0] din ;
wire [3:0] din ;
input [1:0] sel ;
wire [1:0] sel ;

always @ (din or sel) begin
if (sel==0)
dout = din[3];
else if (sel==1)
dout = din[2];
else if (sel==2)
dout = din[1];
else
dout = din[0];
end

endmodule


6 comments :

Unknown said...

sir it's all nice program , but i need testbench for all programs. so can u send me testbench on my mail id? digvijay654@gmail.com

Unknown said...

sir i want 4 to 1 multiplexer using if else statements algorithm and flow chart, if you don't mind plz send soon to my gmail ID:-szanjay1@gmail.com update to this website only. I hope you will help to students

Unknown said...
This comment has been removed by the author.
abbasKara said...

sir why don't you use the wires ?

Anonymous said...

Sir could you please send to this mail ID also 🙏 ID: arshiya.c1@gmail.com

Unknown said...

This progrm algorithm send me sir please

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