Tuesday, 12 November 2013

A Small Discussion about VHDL & Verilog HDL...







A Small Discussion about VHDL & Verilog HDL -


VHDL or Verilog HDL - A small discussion (Verilog HDL with Naresh Singh Dobal learning Series).



Verilog HDL is easier to understand and use, It is very effectively used for simulation and synthesis. but it lacks for system level or complex designing. It is promoted by OVI (Open Verilog International). It is widely used for ASIC designing or lower level design (RTL or  lower), but this results in faster simulation and effective synthesis. Mostly used in North America, Asia & Japan, but not popular in Europe.

As comparable to verilog HDL, VHDL is more complex, thus difficult to learn and use. But this offers more flexibility of designing. Since VHDL is better suited for handling very complex systems, so it is now gaining popularity. VHDL  is mainly promoted by VHDL international. VHDL is relatively weaker in lower designs. But superior in system level design. Many believes that in long terms presents better condition and adaptability than its competitors. This language is widely used in Europe, significantly used in US and Canada, but this disliked in Japan...


Both the HDL's are used to describe electronic systems.
The function of systems is to get input data from it's environment and give output some data in return.
In verilog HDL this is called a module which is a basic building block in Verilog HDL, and in VHDL this is defined in Entity & Architecture Pair.
 Both the Languages are IEEE Standard.


I would love to read your suggestions and comments here below,
Best Regard //
Naresh Singh Dobal
nsdobal@gmail.com


2 comments :

Giri prasad said...

plz send vhdl code for 1:8 &8:1 demultiplexers by using behavior model email:prasadgiri20@gmail.com plz sir

meghdeep kar said...

Sir I have made a program in Verilog HDL of a 32 bit booth multiplier which is module booth_multiplier(a,b,y,sign);
parameter N=32,P=N/2; //N=no. of inputs P= no. Of Groups
output reg sign;
input[N-1:0]a,b; //a= multiplier b= multiplicant
output[(N+N-1):0]y;
integer k,i;
reg[2:0]m[P-1:0];
reg[(N+N-1):0]b1[P-1:0];
reg[(N+N-1):0]z[P-1:0];
reg[(N+N-1):0]z1;
always@(a or b)begin
m[0]={a[1],a[0],1'b0};
for(k=1;k<P;k=k+1)
begin
m[k]={a[2*k+1],a[2*k],a[2*k-1]};
end
for(k=0;k<P;k=k+1)begin
case(m[k])
3'b000:b1[k]=0;
3'b001:b1[k]=b;
3'b010:b1[k]=b;
3'b011:b1[k]=b*2;
3'b100:b1[k]=b*(-2);
3'b101:b1[k]=b*(-1);
3'b110:b1[k]=b*(-1);
3'b111:b1[k]=0;
endcase
z[k]=$signed(b1[k]);
for(i=0;i<k; i=i+1)begin
z[k]={z[k],2'b00};
end
end
z1=z[0];
for(k=1;k<P;k=k+1)begin
z1=z1+z[k];
sign=0;
end
if(z1[2*N-1]==1)begin
z1=(~z1+1'b1);
sign=1;
end
end
assign y=z1;
endmodule

Sir I want to make this 32 bit booth multiplier using Carry Look Ahead Adder.....can you send me the necessary code in my email meghdeepkar@gmail.com. it is very urgent sir...please send the code...

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