Monday, 15 July 2013

Design of 2 : 4 Decoder using Conditional Operator (Verilog CODE).




Design of 2 : 4 Decoder using Conditional Operator (Data Flow Modeling Style).


Output Waveform :  2 : 4 Decoder


Verilog CODE-


//-----------------------------------------------------------------------------
//
// Title       : decoder2_4
// Design      : verilog upload
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : 2 to 4 Decoder using Conditional Operator.v



module decoder2_4 ( din ,dout );

output [3:0] dout ;

input [1:0] din ;

assign dout[3] = din==2'b00 ? 1'b1 : 1'b0;
assign dout[2] = din==2'b01 ? 1'b1 : 1'b0;
assign dout[1] = din==2'b10 ? 1'b1 : 1'b0;
assign dout[0] = din==2'b11 ? 1'b1 : 1'b0;

endmodule

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