Sunday, 21 July 2013

Design of SR (Set - Reset) Flip Flop using Behavior Modeling Style (Verilog CODE).







Design of SR (set-reset) Flip Flop using Behavior Modeling Style -


Output Waveform :   SR (Set Reset) Flip Flop



Verilog CODE-



//-----------------------------------------------------------------------------
//
// Title       : sr_flip_flop
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : SR (set reset) Flip Flop using Behavior Modeling Style.v

module sr_flip_flop ( s ,r ,clk ,reset ,q ,qb );

output q ;
reg q ;
output qb ;
reg qb ;

input s ;
wire s ;
input r ;
wire r ;
input clk ;
wire clk ;
input reset ;
wire reset ;

always @ (posedge (clk)) begin
if (reset) begin
q <= 0;
qb <= 1;
end
else begin
if (s!=r) begin
q <= s;
qb <= r;
end
else if (s==1 && r==1) begin
q <= 1'bZ;
qb <= 1'bZ;
end
end
end


endmodule

1 comments :

sridhar reddy said...

please write test bench with comments sir.......

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