Sunday 21 July 2013

Design of Serial IN - Parallel OUT Shift Register using Behavior Modeling Style (Verilog CODE)-






Design of Serial IN - Parallel Out Shift Register using Behavior Modeling Style -


Output Waveform :   Serial IN - Parallel OUT   Shift Register


Verilog CODE-


//-----------------------------------------------------------------------------
//
// Title       : SIPO
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : Serial IN Parallel OUT  Shift Register using Behavior Modeling Style.v


module SIPO ( din ,clk ,reset ,dout );

output [3:0] dout ;
wire [3:0] dout ;

input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;

reg [3:0]s;

always @ (posedge (clk)) begin
if (reset)
s <= 0;
else begin
s[3] <= din;
s[2] <= s[3];
s[1] <= s[2];
s[0] <= s[1];
end
end

assign dout = s;


endmodule

5 comments :

Unknown said...

Sir, there is no change in din so the 7th element of din will always gets into the serial register.

Unknown said...

please provide testbench.

Unknown said...

Please provide test bench.

Unknown said...

Its not going to work

Unknown said...

Sir please provide test bench

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