Wednesday, 17 July 2013

Design of 4 Bit Adder cum Subtractor using xor Gate and Structural Modeling Style (Verilog CODE).





Design of 4 Bit Adder cum Subtractor using XOR Gate and Structural Modeling Style -







Verilog CODE-


//-----------------------------------------------------------------------------
//
// Title       : adder / subtactor_4bit
// Design      : upload_design1
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : Design of 4 Bit adder cum subtractor using structural modeling style.v


module adder_subtractor_4bit ( a ,b , sel ,dout );

output [3:0] dout ;

input [3:0] a ;
input [3:0] b ;
input sel ;

wire [2:0]s;
wire [3:0]l;

assign l = b ^ {sel,sel,sel,sel};

full_adder u0 (a[0],l[0],sel,dout[0],s[0]);
full_adder u1 (a[1],l[1],s[0],dout[1],s[1]);
full_adder u2 (a[2],l[2],s[1],dout[2],s[2]);
full_adder u3 (a[3],l[3],s[2],dout[3],);

endmodule




//-------------------- Full  Adder  Design ---------------------



//-----------------------------------------------------------------------------
//
// Title       : full_adder
// Design      : verilog upload
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : full adder design.v

 
module full_adder ( a ,b ,c ,dout ,carry );

output dout ;
output carry ;

input a ;
input b ;
input c ;

assign dout = a ^ b ^ c;  
assign carry = (a&b) | (b&c) | (c&a);

endmodule

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