Tuesday 30 July 2013

Design of 8 : 3 Parity Encoder using conditional operator






Design of 8 : 3 Parity Encoder using Conditional Operator -


Output Waveform 1 :  8  to  3 Parity Encoder



Output Waveform  :   8  to  3 Parity Encoder

Verilog CODE -



//-----------------------------------------------------------------------------
//
// Title       : parity_encoder
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Parity Encoder using conditional operator.v


module parity_encoder ( din ,dout );

output [2:0] dout ;
wire [2:0] dout ;

input [7:0] din ;
wire [7:0] din ;

assign dout = din[7] ?  0 :
 din[6] ?  1 :
 din[5] ?  2 :
 din[4] ?  3 :
 din[3] ?  4 :
 din[2] ?  5 :
 din[1] ?  6 :
 din[0] ?  7 : 1'bzzz ;


endmodule

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