Wednesday, 17 July 2013

Design of 2 to 1 Multiplexer using Gate Level Modeling Style (Verilog Code).





Design of 2 to 1 Multiplexer using Gate Level Modeling Style -



Output Waveform  :   2 to 1 Multiplexer




VHDL Code -



//-----------------------------------------------------------------------------
//
// Title       : multiplexer_2_1
// Design      : verilog upload
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : 2  to 1 multiplexer using Gate Level Modeling Style.v


module multiplexer_2_1 ( a ,b ,sel ,dout );

output dout ;

input a ;
input b ;
input sel ;

wire m;
wire n;
wire o;


and u0 (n,m,a);
and u1 (o,b,sel);
not u2 (m,sel);
or u3 (dout,n,o);

endmodule

1 comments :

Rajesh Sahoo said...

the above ocde is not working syntax error .what to do

Post a Comment

 
Design by Wordpress Theme | Bloggerized by Free Blogger Templates | coupon codes