Sunday, 21 July 2013

Design of D-Flip Flop using Behavior Modeling Style (Verilog CODE) -






Design of D-Flip Flop using Behavior Modeling Style -


Output Waveform :   D  Flip Flop


Verilog CODE -



//-----------------------------------------------------------------------------
//
// Title       : d_flip_flop
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : D flip flop using behavior modeling style.v

module d_flip_flop ( din ,clk ,reset ,dout );

output dout ;
reg dout ;

input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;

always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else
dout <= din ;
end

endmodule

2 comments :

Surbhi batavale said...

please give me the verilog code for 8bit D flipflop..

nandini srirambhatla said...

why alwways@(posedge clock)

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