Sunday, 21 July 2013

Design of 1 to 4 Demultiplexer uisng CASE Statements (Behavior Modeling Style) Verilog CODE -







Design of 1 to 4 Demultiplexer using CASE Statements (Behavior Modeling Style) -


Output Waveform :   1 to 4  Demultiplexer


Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : demultiplexer1_4
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : 1 to 4 demultiplexer using case statement.v



module demultiplexer1_4 ( din ,sel ,dout );

output [3:0] dout ;
reg [3:0] dout ;

input din ;
wire din ;
input [1:0] sel ;
wire [1:0] sel ;

always @ (din or sel) begin
case (sel)
0 : dout = {din,3'b000};
1 : dout = {1'b0,din,2'b00};
2 : dout = {2'b00,din,1'b0};
default : dout = {3'b000,din};
endcase
end

endmodule

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