Tuesday, 23 July 2013

Design of MOD-6 Counter using Behavior Modeling Style (Verilog CODE)-






Design of  MOD-6   Counter using Behavior Modeling Style -


Output Waveform :   MOD-6 Counter


Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : counter_mod6
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Design of MOD-6 counter using behavior Modeling Style.v


module counter_mod6 ( clk ,reset ,dout );

output [2:0] dout ;
reg [2:0] dout ;

input clk ;
wire clk ;
input reset ;
wire reset ;

initial dout = 0;

always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else if (dout<5)
dout <= dout + 1;
else
dout <= 0;
end
 
endmodule

1 comments :

Ashmita ece said...

provide testbench too please

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