Monday, 15 July 2013

Full Adder Design using Logical Expression (Verilog CODE)

Full Adder Design using Logical Expression (Data Flow Modeling Style)-


Output Waveforms : Full Adder

Program-


//-----------------------------------------------------------------------------
//
// Title       : full_adder
// Design      : vhdl_test
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : Full Adder using Logical Expression.v



module full_adder ( a ,b ,c ,sum ,carry );

output sum ;
output carry ;

input a ;
input b ;
input c ;


assign sum = a ^ b ^ c;
assign carry = (a&b) | (b&c) | (c&a);

endmodule

5 comments :

Neerigatti Somasekhar said...

sir i want structural model

Neerigatti Somasekhar said...

sir i want structural model

naveen kumar said...

FULL ADDER STRUCTURAL


module fl_st(a,b,cin,sum,carry) ;
input a,b,cin; // input variables
output carry,sum; // output variables
wire w0,w2,w3; // internal variables declaration
xor g1(w0,a,b);
xor g2(sum,w0,cin); //sum
and g3(w3,a,b);
and g4(w2,w0,cin);
or g5(carry,w3,w2); //carry
endmodule

dorababu said...

how can we write 3 bit full adder dut and tb...

Siva Nageswararao said...

sir,I want behavioural model using case statement

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