Sunday, 21 July 2013

Design of SR Latch using Behavior Modeling Style (Verilog CODE)





Design of SR Latch using Behavior Modeling Style -


Output Waveform :   SR (set-reset) Latch



Verilog CODE-


//-----------------------------------------------------------------------------
//
// Title       : SR_Latch
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : SR latch using Behavior Modeling Style.v



module SR_Latch ( s ,r ,enable ,reset ,q ,qb );

output q ;
reg q ;
output qb ;
reg qb ;

input s ;
wire s ;
input r ;
wire r ;
input enable ;
wire enable ;
input reset ;
wire reset ;

always @ (enable or s or r or reset) begin
if (reset) begin
q = 0;
qb = 1;
end else if (enable) begin
if (s!=r) begin
q = s;
qb = r;
end else if (s==1 && r==1) begin
q = 1'bZ;
qb = 1'bZ;
end
end
end

endmodule

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