Sunday, 21 July 2013

Design of Serial IN - Serial OUT Shift Register using Behavior Modeling Style (Verilog CODE) -






Design of Serial IN - Serial OUT Shift Register using Behavior Modeling Style -


Output Waveform :   Serial IN - Serial OUT  Shift Register



Verilog CODE-



//-----------------------------------------------------------------------------
//
// Title       : Serial_in_Serial_out
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : Serial IN - Serial OUT shift register using Behavior Modeling Style.v



module Serial_in_Serial_out ( din ,clk ,reset ,dout );

output dout ;
reg dout ;

input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;

reg [2:0]s;

always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else begin
s[0] <= din ;
s[1] <= s[0] ;
s[2] <= s[1] ;
dout <= s[2];
end
end

endmodule

4 comments :

Jonathan Prodduku said...

Is the array required [2:0] or [3:0]????

Jonathan Prodduku said...

ok i thought it was a 4bit reg code but it was not mentioned in the title

Abhijit Mondal said...
This comment has been removed by the author.
Abhijit Mondal said...

it is a 3bit code right?

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