Monday, 15 July 2013

Half Subtractor Design using Logical Expression (Verilog CODE).

Half Subtractor Design using Logical Expression (Data Flow Modeling Style)-

Output WaveForm : Half Subtractor

Program-



//-----------------------------------------------------------------------------
//
// Title       : half_subtractor
// Design      : verilog upload
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : Half Subtractor using Logical Gates.v



module half_subtractor ( a ,b ,diff ,borrow );

output diff ;
output borrow ;

input a ;
input b ;

assign diff = a ^ b;
assign borrow = (~a) & b;


endmodule

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