Tuesday, 23 July 2013

Design of Frequency Divider (Divide by 10) using Behavior Modeling Style (Verilog CODE) -






Design of Frequency Divider (Divide by 10) using Behavior Modeling Style -



Output Waveform :   Frequency Divider (Divide by 10).


Verilog CODE -



//-----------------------------------------------------------------------------
//
// Title       : frquency_divider_by10
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Design of frequency Divider (divide by 10).v


module frquency_divider_by10 ( clk ,out_clk );

output out_clk ;
reg out_clk ;

input clk ;
wire clk ;

reg [3:0] m;

initial m = 0;

always @ (posedge (clk)) begin
if (m<9)
m <= m + 1;
else
m <= 0;
end

always @ (m) begin
if (m<5)
out_clk <= 1;
else
out_clk <= 0;
end


endmodule

4 comments :

Unknown said...

Hi. Do you have the test bench for this?

navyashree hk said...

hi,can you help me out to write a verilog code to divide 430Mhz(input) by 43

Unknown said...

design a mod43 counter

Unknown said...

can u explain me the code??

Post a Comment

 
Design by Wordpress Theme | Bloggerized by Free Blogger Templates | coupon codes