Monday, 15 July 2013

4 : 2 Encoder using Logical Gates (Verilog CODE).

4 : 2 Decoder Design using Logical Gates (Data Flow Modeling Style)-



Output Waveform :   4 : 2 Decoder


Verilog CODE -



//-----------------------------------------------------------------------------
//
// Title       : encoder4_2
// Design      : verilog upload
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : 4 to 2 Encoder Design using Logical Gates.v



module encoder4_2 ( a ,b ,c ,d ,x ,y );

output x ;
output y ;

input a ;
input b ;
input c ;
input d ;

assign x = b | d;
assign y = c | d;

endmodule

6 comments :

Tim Mac said...

why is the input 'a' never used?

saurav ganguly said...

why is the input 'a' never used?

saurav ganguly said...

why is the input 'a' never used?

Stranger said...

thank you sir for your wonderful work

sainu said...

thank you

sainu said...

thank you

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