Wednesday, 17 July 2013

Design of Parallel IN - Parallel OUT Shift Register using Structural Modeling Style (Verilog CODE).





Design of Parallel IN  -  Parallel OUT Shift Register using Structural Modeling Style



Output Waveform  :   Parallel IN  -  Parallel OUT   Shift Register


Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : pipo
// Design      : upload_design1
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : Design of Parallel In - Parallel Out Shift Register using d_flip flop.v


module sipo ( din ,clk ,reset ,dout );

output [3:0]dout ;

input [3:0]din ;
input clk ;
input reset ;  
wire [3:0]s;

d_flip_flop u0 (.din(din[0]),
.clk(clk),
.reset(reset),
.dout(dout[0]));


d_flip_flop u1 (.din(din[1]),
.clk(clk),
.reset(reset),
.dout(dout[1]));


d_flip_flop u2 (.din(din[2]),
.clk(clk),
.reset(reset),
.dout(dout[2]));


d_flip_flop u3 (.din(din[3]),
.clk(clk),
.reset(reset),
.dout(dout[3]));


endmodule




// -------------- D flip flop  design - -----------------------



//-----------------------------------------------------------------------------
//
// Title       : d_flip_flop
// Design      : upload_design1
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : d_flip_flop.v



module d_flip_flop ( din ,clk ,reset ,dout );

output dout ;
reg dout;

input din ;
input clk ;
input reset ;

always @ (posedge clk)
begin
if (reset)
dout <= 1;
else
dout <= din;
end

endmodule

1 comments :

Ayyappan N said...

can u write this code in other way

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