Sunday, 21 July 2013

Design of Toggle Flip Flop using Behavior Modeling Style (Verilog CODE) -






Design of Toggle Flip Flop using Behavior Modeling Style -


Output Waveform :  Toggle Flip Flop



Verilog CODE-



//-----------------------------------------------------------------------------
//
// Title       : t_flip_flop
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : Toggle Flip Flop using Behavior Modeling Style.v


module t_flip_flop ( t ,clk ,reset ,dout );

output dout ;
reg dout ;

input t ;
wire t ;
input clk ;
wire clk ;
input reset ;
wire reset ;

initial dout = 0;

always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else begin
if (t)
dout <= ~dout;
end
end

endmodule

5 comments :

Mark Suvi said...

what about negative edge?

srikant karwa said...

this is syncronous....
if it is asyncronous then go for
always@(posedge clock or negedge reset)
begin
if(reset)
dout <= 1'b0;
else
dout <= ~dout;
end

srikant karwa said...
This comment has been removed by the author.
Unknown said...

im getting errors in quartus tool

N Dilip Kumar said...

im getting errors in quartus tool

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