Monday, 15 July 2013

Design of BCD to 7 Segment Driver for Common Cathode using Conditional Operator (Verilog CODE).




Design of BCD to 7 Segment Driver for Common Cathode Display using Conditional Operator (Data Flow Modeling Style).

Output Waveform :   BCD to 7 segment Driver for Common Cathode Display.



Verilog CODE-



//-----------------------------------------------------------------------------
//
// Title       : bcd_to_7segment_CK
// Design      : verilog upload
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : 7 segment driver for common cathode using conditional operator.v



module bcd_to_7segment_CK ( bcd ,seg7 );

output [6:0] seg7 ;

input [2:0] bcd ;

    assign seg7 = (bcd==0) ? 7'b1111110 :
            (bcd==1) ? 7'b0110000 :
            (bcd==2) ? 7'b1101101 :
            (bcd==3) ? 7'b1111001 :
            (bcd==4) ? 7'b0110011 :
            (bcd==5) ? 7'b1011011 :
            (bcd==6) ? 7'b0011111 :
            (bcd==7) ? 7'b1110000 :
            (bcd==8) ? 7'b1111111 :
            (bcd==9) ? 7'b1110011 :
            7'b0000000 ;

endmodule

2 comments :

iftikhar ali said...

stimulus plz????

Muhammad Uzair Arif said...

module stimulus;
wire [6:0]seg7;
reg [3:0] bcd;
bcd_to_7segment_CK c1(seg7 ,bcd );
initial
begin
bcd=0;
#10 bcd=1;
#10 bcd=2;
#10 bcd=3;
#10 bcd=4;
#10 bcd=5;
#10 bcd=6;
#10 bcd=7;
#10 bcd=8;
#10 bcd=9;
#10 $stop;
#10 $finish;
end
endmodule


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