Sunday, 21 July 2013

Small Description about Behavior Modeling Style in Verilog HDL.

Behavior Modeling Style -

  • Behavior Modeling Style shows that how our system performs according to current input values.
  • In behavior Modeling, we defines that what value we get at the output corresponding to input values.
  • We Defines the function / Behavior of our Digital Systems in Behavior Modeling Style.
  • Behavior Modeling Style works on Sequential Execution.
  • Behavior Modeling style very much similar to C-language.

PROCEDURAL BLOCKS   are the basic building blocks to work on Behavior modeling style.   initial     &     always       are the keyword which converts the way of execution from concurrent execution to sequential execution. 

Syntax - How to use   initial    keyword in Verilog HDL Language.

initial Block -    

Initial Block mainly used in Test Benches and also at those places where our current output depends on the last output and we have to initialize some value to start execution.

initial begin   

        Sequential Statements ; 


always Block  -     

Always Block,   As name specifies always Block executes multiple times, We have two methods to trigger the execution of always Block.
  • Event based Triggering.  (Depends on the change in signal values).
  • Time based Triggering.   (Depends on the time specified).

Syntax - How to use   always    keyword in Verilog HDL Language.

always  @   (Senstivity List) 

        Sequential Statements ; 


All the statements in behavior modeling style must be written in between  concurrent & Sequential   block.

Sequential Block -


Parallel Block -


Behavior Modeling Style Statements -

Sample Programs & LAB Exercise -

Basic Combinational Circuits Design.-

Basic Flip flop Design using Behavior Modeling Style -

Shift Registers Design using Behavior Modeling Style -

Sample Programs for Loops Statements -

Sample Programs for Basic Systems using Verilog HDL -


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