Monday, 15 July 2013

Design of 1 Bit Comparator using Logical Gates (Verilog CODE).

Design of 1 Bit Comparator using Logical Gates (Data Flow Modeling Style) -


Output Waveform :    1 Bit Comparator

Verilog CODE-



//-----------------------------------------------------------------------------
//
// Title       : comparator_1bit
// Design      : verilog upload
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : 1 bit comparator using logical gates.v



module comparator_1bit ( a ,b ,equal ,greater ,lower );

output equal ;
output greater ;
output lower ;

input a ;
input b ;

assign equal = a ~^ b;
assign lower = (~a) & b;
assign greater = a & (~b);

endmodule

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