Monday, 15 July 2013

Conditional Operator (Data Flow Modeling Style) Verilog HDL



Conditional Operator (Ternary Operator) in Verilog HDL   (Data Flow Modeling Style) -




Syntax -


Method -1  (Condition)  -

assign     target    =     (Condition)     ?      (True)     :
                                                                    (False)  ;


Method -2   (Nets) -

assign     target    =     (Net)     ?      (Value_1)     :
                                                           (Value_0)  ;





Sample Programs-


1 comments :

Shahwaiz bin Javed said...

can i form 2x4 decoder using conditional operator???

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