Wednesday 17 July 2013

Design of Serial In - Serial Out Shift Register using D Flip Flop (Structural Modeling Style) (Verilog CODE).





Design of Serial IN  - Serial OUT Shift Register using  D Flip Flop (Structural Modeling Style)..

Output Waveform :  Serial IN  -  Serial OUT Shift Register



Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : siso
// Design      : upload_design1
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : Design of Serial In - Serial Out Shift Register using d_flip flop.v


module siso ( din ,clk ,reset ,dout );

output dout ;

input din ;
input clk ;
input reset ;  
wire [2:0]s;

d_flip_flop u0 (.din(din),
.clk(clk),
.reset(reset),
.dout(s[0]));


d_flip_flop u1 (.din(s[0]),
.clk(clk),
.reset(reset),
.dout(s[1]));


d_flip_flop u2 (.din(s[1]),
.clk(clk),
.reset(reset),
.dout(s[2]));


d_flip_flop u3 (.din(s[2]),
.clk(clk),
.reset(reset),
.dout(dout));


endmodule




// -------------- D flip flop  design - -----------------------



//-----------------------------------------------------------------------------
//
// Title       : d_flip_flop
// Design      : upload_design1
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : d_flip_flop.v



module d_flip_flop ( din ,clk ,reset ,dout );

output dout ;
reg dout;

input din ;
input clk ;
input reset ;

always @ (posedge clk)
begin
if (reset)
dout <= 1;
else
dout <= din;
end

endmodule

4 comments :

Unknown said...

how to write the test bench for the shift register......please help me....

Unknown said...

module testregister();
wire Q;
reg d,clk;
shiftregister s1(Q,d,clk);
initial
begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
d=0;
#10 d=1;
#2 d=0;
#5 d=1;
#10 d=0;
#3 d=1;
#4 d=0;
end
endmodule

Unknown said...

How to write verilog code for 16 bit 2's complement serial subtrator... Plzz help

Unknown said...

How to write verilog code for 16 bit 2's complement serial subtrator... Plzz help

Post a Comment

 
Design by Wordpress Theme | Bloggerized by Free Blogger Templates | coupon codes