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2 : 4 Decoder Design using Logical Gates (Data Flow Modeling Style).
Verilog CODE-
//-----------------------------------------------------------------------------
//
// Title : decoder2_4
// Design : verilog upload
// Author : Naresh Singh Dobal
// Company : nsd
//
//-----------------------------------------------------------------------------
//
// File : 2 : 4 Decoder using Logical Gates.v
module decoder2_4 ( a ,b ,w ,x ,y ,z );
output w ;
output x ;
output y ;
output z ;
input a ;
input b ;
assign w = (~a) & (~b);
assign x = (~a) & b;
assign y = a & (~b);
assign z = a & b;
endmodule
 |
| Output Waveform : 2 to 4 Decoder |
Verilog CODE-
//-----------------------------------------------------------------------------
//
// Title : decoder2_4
// Design : verilog upload
// Author : Naresh Singh Dobal
// Company : nsd
//
//-----------------------------------------------------------------------------
//
// File : 2 : 4 Decoder using Logical Gates.v
module decoder2_4 ( a ,b ,w ,x ,y ,z );
output w ;
output x ;
output y ;
output z ;
input a ;
input b ;
assign w = (~a) & (~b);
assign x = (~a) & b;
assign y = a & (~b);
assign z = a & b;
endmodule
5 comments :
what about enable bit ???????????????/
http://www.rfwireless-world.com/source-code/VERILOG/2-to-4-decoder-verilog-code.html
It's not completd yet
Mudichu podungada
Olunga podunga da adichu ethanum :/
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