Design of BCD to 7 Segment Driver for Common Cathode Display using case statement (Verilog Code) -

Design of BCD to 7 Segment Driver for Common Cathode Display using CASE Statement (Behavior Modeling Style) -

Output Waveform :   BCD to 7 Segment Driver for Common Cathode Display.

Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : BCD_to_7Seg
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : BCD to 7 Segment Driver for common cathode display using case.v

module BCD_to_7Seg ( bcd , seg7 );

output [6:0] seg7 ;
reg [6:0] seg7 ;

input [3:0] bcd ;
wire [3:0] bcd ;


always @ (bcd) begin
case (bcd)
0 : seg7 = 7'b1111110;
1 : seg7 = 7'b0110000;
2 : seg7 = 7'b1101101;
3 : seg7 = 7'b1111001;
4 : seg7 = 7'b0110011;
5 : seg7 = 7'b1011011;
6 : seg7 = 7'b0011111;
7 : seg7 = 7'b1110000;
8 : seg7 = 7'b1111111;
9 : seg7 = 7'b1110011;
default : seg7 = 7'b0000000;
endcase
end

endmodule