Half Adder Design using Logical Expressions (Verilog CODE)

Half Adder Design using Logical Expressions (Data Flow Modeling Style)-

Output Waveform : Half Adder

Verilog CODE -



//-----------------------------------------------------------------------------
//
// Title       : half_adder
// Design      : vhdl_test
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : Half Adder Using Logical Gates.v



module half_adder ( a ,b ,sum ,carry );

output sum ;
output carry ;

input a ;
input b ;

assign sum = a ^ b;
assign carry = a & b;

endmodule