Design of 8 - nibble STACK using Behavior Modeling Style -
Output Waveform : 8 ibble STACK Design |
Verilog CODE -
//-----------------------------------------------------------------------------
//
// Title : stack_8nibble
// Design : verilog upload 4
// Author : Naresh Singh Dobal
// Company : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File : Design of 8 nibble stack using behavior modeling style.v
module stack_8nibble ( clk ,push ,pull ,din ,dout );
output [3:0] dout ;
reg [3:0] dout ;
input clk ;
wire clk ;
input push ;
wire push ;
input pull ;
wire pull ;
input [3:0] din ;
wire [3:0] din ;
reg [3:0] stack [0:7] ;
reg [3:0] i;
initial i = 0;
always @ (posedge (clk)) begin
if (push) begin
stack[i] <= din;
i <= i + 1;
end else if (pull) begin
dout <= stack[i];
i <= i - 1;
end
end
endmodule
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