Simple AND Gate Design using Verilog HDL

A Simple AND Gate Design using Logical Expression (Data Flow Modeling Style)-

Output Waveform : AND Gate

Verilog Code-


//-----------------------------------------------------------------------------
//
// Title       : AND_Gate
// Design      : vhdl_test
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : AND Gate.v



module AND_Gate ( a ,b ,dout );

output dout ;
input a ;
input b ;

assign dout = a & b;

endmodule