Design of 4 Bit Adder cum Subtractor using Structural Modeling Style (Verilog CODE).

Design of 4 Bit Adder cum Subtractor using Structural Modeling Style-

Output Waveform :  4 Bit Adder / Subtractor

Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : adder_subtactor_4bit
// Design      : upload_design1
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : Design of 4 Bit adder cum subtractor using structural modeling style.v


module adder_subtactor_4bit ( a ,b ,sel ,dout );

output [3:0] dout ;

input [3:0] a ;
input [3:0] b ;
input sel ;

wire [3:0]m;
wire [3:0]n;


adder_4bit u0  (.a (a),
.b (b),
.sum (m));

subtractor_4bit u1 (.a(a),
.b(b),
.diff (n));

mux_4bit u2 (.a(m),
.b(n),
.sel(sel),
.dout(dout));


endmodule





//--------------------- Design of 4 bit adder -------------------



//-----------------------------------------------------------------------------
//
// Title       : adder_4bit
// Design      : verilog upload
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : Design of 4 Bit Adder using 4 Full adder (Structural Modeling Style).v


module adder_4bit ( a ,b ,sum ,carry );

output [3:0] sum ;
output carry ;

input [3:0] a ;
input [3:0] b ;

wire [2:0]s;

full_adder u0 (a[0],b[0],1'b0,sum[0],s[0]);
full_adder u1 (a[1],b[1],s[0],sum[1],s[1]);
full_adder u2 (a[2],b[2],s[1],sum[2],s[2]);
full_adder u3 (a[3],b[3],s[2],sum[3],carry);

endmodule




//-------------- 4 bit subtractor --------------------

// Title       : Subtractor_4bit
// Design      : verilog upload
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : Design of 4 Bit Subtractor using Structural Modeling Style.v


module subtractor_4bit ( a ,b ,diff ,borrow );

output [3:0] diff ;
output borrow ;

input [3:0] a ;
input [3:0] b ;

wire [2:0]s;
wire [3:0]l;

full_adder u0 (a[0],l[0],1'b1,diff[0],s[0]);
full_adder u1 (a[1],l[1],s[0],diff[1],s[1]);
full_adder u2 (a[2],l[2],s[1],diff[2],s[2]);
full_adder u3 (a[3],l[3],s[2],diff[3],borrow);

endmodule



//-------------------- Full  Adder  Design ---------------------


//-----------------------------------------------------------------------------
//
// Title       : full_adder
// Design      : verilog upload
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : full adder design.v


module full_adder ( a ,b ,c ,sum ,carry );

output sum ;
output carry ;

input a ;
input b ;
input c ;

assign sum = a ^ b ^ c;
assign carry = (a&b) | (b&c) | (c&a);

endmodule




//-------------- 2 : 1 Multiplexer (4 bit)  Design ------------


//-----------------------------------------------------------------------------
//
// Title       : 2 : multiplexer
// Design      : verilog upload
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : 2 to 1 Multiplexer.v


module mux_4bit ( a ,b , sel, dout );

output [3:0]dout ;

input [3:0]a ;
input [3:0]b ;
input sel ;

assign dout = sel ? b : a;

endmodule