Modeling Styles in Verilog HDL

Modeling Styles in Verilog HDL -


Modeling Style means, that how we Design our Digital IC's in Electronics. With the help of modeling style we describe the Design of our Electronics.
Normally we use Three type of Modeling Style in Verilog HDL -

• Data Flow Modeling Style.
• Structural Modeling Style.
• Behavior Modeling Style.

Data Flow Modeling Style -

• Data Flow Modeling Style Shows that how the data / signal flows from input to ouput threw the registers / Components. 
• Data Flow Modeling Style works on Concurrent Execution.

Structural Modeling Style -

• Structural Modeling Style shows the Graphical Representation of modules/ instances / components with their Interconnection. 
• In Structural Modeling Style We defines that how our Components / Registers / Modules are Connected to each other using Nets/ Wires. 
• Structural Modeling Style is based on Net-List Language.
• Structural Modeling Style works on Concurrent Execution.

Behavior Modeling Style -

• Behavior Modeling Style shows that how our system performs according to current input values.
• In behavor Modeling, we defines that what value we get at the output corresponding to input values.
• We Defines the function / Behavior of our Digital Systems in Behavior Modeling Style.
• Behavior Modeling Style works on Sequential Execution.