Design of 8 to 3 Parity Encoder using if -else statements (Verilog CODE)

Design of 8 to 3 Parity Encoder using if - else statements -

Output Waveform 1 :  8 to 3 Parity Encoder

Output Waveform :  8 to 3 Parity Encoder

Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : parity_encoder
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Parity Encoder using if else statement.v


module parity_encoder ( din ,dout );

output [2:0] dout ;
reg [2:0] dout ;

input [7:0] din ;
wire [7:0] din ;


always @ (din) begin
if (din[7])
dout = 0;
else if (din[6])
dout = 1;
else if (din[5])
dout = 2;
else if (din[4])
dout = 3;
else if (din[3])
dout = 4;
else if (din[2])
dout = 5;
else if (din[1])
dout = 6;
else if (din[0])
dout = 7;
else
dout = 3'bZZZ;
end

endmodule