Design of BCD to 7 Segment Driver using IF-ELSE Statements (Behavior Modeling Style) (Verilog CODE)-

Design of  BCD to 7 Segment Driver using if-else statement (Behavior Modeling Style)-

Output Waveform :    BCD to 7 Segment Driver for common anode display

Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : BCD_to_7seg
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : BCD to 7 Segment Driver for common anode display using if else.v



module BCD_to_7seg ( bcd ,seg7 );

output [6:0] seg7 ;
reg [6:0] seg7 ;

input [3:0] bcd ;
wire [3:0] bcd ;

always @ (bcd) begin
if (bcd==0)
seg7 = 7'b0000001;
else if (bcd==1)
seg7 = 7'b1001111;
else if (bcd==2)
seg7 = 7'b0010010;
else if (bcd==3)
seg7 = 7'b0000110;
else if (bcd==4)
seg7 = 7'b1001100;
else if (bcd==5)
seg7 = 7'b0100100;
else if (bcd==6)
seg7 = 7'b1100000;
else if (bcd==7)
seg7 = 7'b0001111;
else if (bcd==8)
seg7 = 7'b0000000;
else if (bcd==9)
seg7 = 7'b0001100;
else
seg7 = 7'b1111111;
end

endmodule