Design of Frequency Divider (Divide by 4) using Behavior Modeling Style (Verilog CODE)-

Design of Frequency Divider (Divide by 4) using Behavior Modeling Style -

Output Waveform :   Frequency Divider (Divide by 4).

Verilog CODE -



//-----------------------------------------------------------------------------
//
// Title       : frequency_divider_by4
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Design of frequency divider (divide by 4).v


module frequency_divider_by4 ( clk ,out_clk );

output out_clk ;
wire out_clk ;

input clk ;
wire clk ;

reg [1:0]m;

initial m = 0;

always @ (posedge (clk)) begin
m <= m + 1;
end

assign out_clk = m[1];

endmodule